The Verilog Hardware Description Language was first introduced in 1984. Over the 20 year history of Verilog, every Verilog engineer has developed his own personal “bag of tricks” for coding with Verilog. These tricks enable modeling or verifying designs more easily and more accurately. Developing this bag of tricks is often based on years of trial and error. Through experience, engineers learn that one specific coding style works best in some circumstances, while in another situation, a different coding style is best. As with any high-level language, Verilog often provides engineers several ways to accomplish a specific task. Wouldn’t it be wonderful if an engineer first learning Verilog could start with another engineer’s bag of tricks, without having to go through years of trial and error to decide which style is best for which circumstance? That is where this book becomes an invaluable resource. The book presents dozens of Verilog tricks of the trade on how to best use the Verilog HDL for modeling designs at various level of abstraction, and for writing test benches to verify designs. The book not only shows the correct ways of using Verilog for different situations, it also presents alternate styles, and discusses the pros and cons of these styles.

PREFACE The increasing demand on high data rate and quality of service in wireless communication has to cope with limited bandwidth and energy resources. More than 50 years ago, Shannon has paved the way to optimal usage of bandwidth and energy resources by bounding the spectral efficiency vs. signal to noise ratio trade-off. However, as any information theorist, Shannon told us what is the best we can do but not how to do it [1]. In this view, turbo codes are like a dream come true: they allow approaching the theoretical Shannon capacity limit very closely. However, for the designer who wants to implement these codes, at first sight they appear to be a nightmare. We came a huge step closer in striving the theoretical limit, but see the historical axiom repeated on a different scale: we know we can achieve excellent performance with turbo codes, but not how to realize this in real devices.

An Experimental Approach to CDMA and Interference Mitigation was written with the admittedly ambitious intent of filling the gap between communication theory and VLSI implementation, and thus to provide a more general/theoretical approach to the design, development, and testing of a CDMA receiver. As a consequence, the concepts and techniques that are presented turn out to be applicable to a more general kind of digital wireless modems in terms of receiver architecture design and implementation.

Wireless Local Area Networks (WLANs) experience a growing popularity recently. Where WLANs were primarily used for niche applications in the past, they are now deployed as wireless extensions to computer networks. The increase of the datarates from 2 Mbps up to 11 Mbps for roughly a constant price has played a major role in this breakthrough. As a consequence, an even greater success can be envisioned for the more recent OFDM-based WLAN standards in the 5 GHz band, which offer up to 54 Mbps. At IMEC we have realised this potential already several years ago and have established a successful research programme on OF- based WLAN. In 1995, we started our research on wireless OFDM in the frame of a - operation project with SAIT, a Belgian telecom company. The goal of the project was to establish a robust network for industrial environments. This resulted in a first OFDM chip, supporting QPSK, for wireless networking at the end of the project (1999). 1999 was also the start of an intense co-operation with National Semiconductor Inc., which resulted in a second generation ASIC in 2000. This OFDM processor supports up to QAM-64 and has a more optimal channel estimation algorithm.

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers.
High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

This book covers all main aspects of guidance information processing technologies for airborne optical imaging seekers, including theoretical models; image pre-processing; automatic target detection, recognition and tracking; and embedded real-time processing systems.

Processor Design addresses the design of different types of embedded, firmware-programmable computation engines. Because the design and customization of embedded processors has become a mainstream task in the development of complex SoCs (Systems-on-Chip), ASIC and SoC designers must master the integration and development of processor hardware as an integral part of their job. Even contemporary FPGA devices can now accommodate several programmable processors. There are many different kinds of embedded processor cores available, suiting different kinds of tasks and applications.

Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’.